The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices having functional logic circuits therein that can be selectively disposed in active and power saving sleep modes of operation.
Integrated circuit devices that are fabricated using deep sub-micron (DSM) process technologies typically include MOS transistors having thinner gate oxides and lower threshold voltages (Vth). The use of DSM process technologies also typically increase device integration. Unfortunately, the achievement of higher integration levels and lower threshold voltages typically results in higher leakage currents because the magnitude of total leakage current is typically directly proportional to integration density and inversely proportional to threshold voltage. Thus, a simultaneous increase in integration density and decrease in threshold voltage can result in significant increases in leakage currents. One conventional technique for reducing total leakage current within an integrated circuit device is to provide MOS transistors having relatively high threshold voltages (xe2x80x9chigh-Vthxe2x80x9d) for some circuits within the device and MOS transistors having relatively low threshold voltages (low-Vth) for other circuits within the device. For example, high-Vth MOS transistors may be used for circuits that are not critical to timing and low-Vth MOS transistors, which typically have greater leakage, may be used for circuits that are critical for timing. Another conventional technique for reducing total leakage current includes use of a body voltage(s) on an integrated circuit chip as a way to increase effective threshold voltages for certain devices therein.
A technique for reducing leakage current is also described in U.S. Pat. No. 6,064,223 to Lu et al., entitled xe2x80x9cLow Leakage Circuit Configuration for Mosfet Circuits.xe2x80x9d In this patent, at least one switchable pathway is provided between an active circuit and a power or ground node. This switchable pathway, which is provided by PMOS transistor 102 and/or NMOS transistor 108 in FIG. 2 of the ""223 patent, is operable to reduce leakage current through the circuit by essentially disconnecting a power supply path from the circuit. One of many limitations with this technique is the requirement 120 that the switchable pathway be sufficiently large to provide a sufficiently low resistance path to the circuit when the circuit is operating in a high current active mode. However, the use of one or more large switchable pathways may, among other things, reduce integrated densities and complicate efficient layout of the circuit. U.S. Pat. No. 6,081,135 to Goodnow et al., entitled xe2x80x9cDevice and Method to Reduce Power Consumption in Integrated Semiconductor Devices,xe2x80x9d reduces power by eliminating unnecessary node toggling. Unneeded Node toggling is reduced by utilizing either a PMOS pull-up transistor or an NMOS pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which a circuit is inactive. In an illustrated embodiment, the inputs to a circuit are all pulled high after a time of inactivity. This time of inactivity is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption may be reduced without excessive power caused by the pulling itself. Unfortunately, this node toggling technique may reduce integration density by requiring significant on-chip timing and node pulling circuitry.
Thus, notwithstanding these conventional techniques to reduce leakage currents in highly integrated circuits, there continues to be a need for improved techniques that provide efficient current leakage control and do not require extensive on-chip circuitry.
An integrated circuit device according to one embodiment of the present invention utilizes on-chip power down control circuitry to control the timing of application of at least one external power signal to the device when a functional logic circuit within the device is switching in and out of an inactive mode of operation, such as a sleep mode. The at least one external power signal may be provided by one or more power transistors operating in response to signals generated by external power transistor control circuitry. These power transistors may provide power to respective power supply pins that are coupled on-chip to the device and the external power transistor control circuitry may be responsive to one or more signals generated by the device.
In particular, an integrated circuit device is preferably provided having at least one internal (e.g., on-chip) functional logic circuit therein. This internal functional logic circuit may be configurable in a respective active mode of operation or a power-saving sleep mode of operation. The internal functional logic circuit may also include an output at which a respective sleep mode request can be generated. In this case, the internal functional logic circuit may include circuitry that enables the functional logic circuit to generate its own sleep mode request. Functional logic circuits that are capable of generating their own sleep mode request include microprocessor, cache and LCD controller. According to other embodiments, a sleep mode request for a respective internal functional logic circuit may be generated external to the functional logic circuit. Such requests may be generated by other on-chip circuitry or circuitry located external to the device. The device is also preferably provided with an internal (i.e., on-chip) power control logic circuit that generates one or more power down signals. The power down signals may be provided to the external power transistor control circuitry and may be generated in direct response to the sleep mode request.
According to another embodiment of the present invention, an integrated circuit device comprises a plurality of internal functional logic circuits having respective active and power-saving sleep modes of operation. These internal functional logic circuits have first outputs at which respective sleep mode requests are generated. An internal power control logic circuit is also provided. This internal power control logic circuit generates respective power down signals in response to the sleep mode requests generated at the first outputs. These power down signals are provided external to the device. The device may also include a plurality of power supply pads that receive a respective plurality of external power supply signals, with each of the plurality of external power supply signals being provided to a respective one (or more) of the plurality of internal functional logic circuits. In particular, the power down signals generated by the internal power control logic circuit are preferably provided to external power switching circuitry that is electrically coupled to the plurality of power supply pads. The logic value of each of the power down signal can be used to influence whether the external power switching circuitry provides power to or withholds power from respective power supply pads.
According to a preferred aspect of this embodiment, the external power switching circuitry includes a power transistor control circuit that is responsive to the power down signals and a plurality of power transistors that are coupled to the power transistor control circuit and generate the external power supply signals. Moreover, the internal power control logic circuit may comprise an active mode restart control circuit having an output at which respective active restart signals are generated. Each of the plurality of internal functional logic circuits may be responsive to a respective active restart signal generated by the active mode restart control circuit. The logic value of the active restart signal can be used to control whether a respective functional logic circuit is switched from an active mode of operation to a sleep mode of operation and vice versa.
An additional embodiment of the present invention may include a system of integrated circuits. This system may include an integrated circuit chip and power switching circuitry that is located external to the integrated circuit chip. In this embodiment, a device on the chip preferably includes an internal functional logic circuit and an internal power control logic circuit. The internal functional logic circuit has two modes of operation. These two modes of operation include a normal active mode of operation and a power-saving sleep mode of operation, which can be initiated in response to a sleep mode request. The sleep mode request may be generated by the internal functional logic circuit or another circuit internal to the device. The sleep mode request may also be generated external to the device. The internal power control logic circuit performs operations to generate a power down signal in response to the sleep mode request. An active/sleep mode power supply pad is also preferably provided on the integrated circuit chip and this pad is preferably electrically coupled to the internal functional logic circuit. External power switching circuitry is also provided. The power switching circuitry selectively provides power to or withholds power from the active/sleep mode power supply pad in response to the power down signal generated by the internal power control logic circuit. The power switching circuitry may comprise a power transistor control circuit that is responsive to the power down signal and a power transistor that is electrically coupled to the power transistor control circuit and electrically coupled to the active/sleep mode power supply pad.